I. Field of the Disclosure
The technology of the disclosure relates generally to resistive memory, and particularly to write driver circuits for performing write operations in resistive memory arrays.
II. Background
Processor-based computer systems include memory for data storage. Memory systems are composed of memory bitcells capable of storing data, wherein the form of the stored data depends on the type of memory employed. Magnetoresistive random access memory (MRAM) is an example of non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) of an MRAM bitcell. Data is stored in an MTJ as a magnetic state, wherein no electric current is required to preserve a stored data value. Thus, an MTJ can store data even when power is not supplied to the MTJ. Conversely, memory that stores data in the form of an electric charge, such as a static random access memory (SRAM), requires power to preserve a stored data value. Thus, because an MTJ may store information even when power is turned off, particular circuits and systems may benefit from employing MRAM.
In this regard, FIG. 1 illustrates an exemplary MRAM bitcell 10 that includes a metal-oxide semiconductor (typically n-type MOS, i.e., NMOS) access transistor 12 integrated with an MTJ 14 for storing non-volatile data. The MRAM bitcell 10 may be provided in an MRAM memory used as memory storage for any type of system requiring electronic memory, such as a central processing unit (CPU) or a processor-based system, as examples. The MTJ 14 includes a pinned layer 16 and a free layer 18 disposed on either side of a tunnel barrier 20 formed by a thin non-magnetic dielectric layer. When the magnetic orientation of the pinned layer 16 and the free layer 18 are anti-parallel (AP) to each other, an AP state exists (e.g., a logical ‘1’). When the magnetic orientation of the pinned layer 16 and the free layer 18 are parallel (P) to each other, a P state exists (e.g., a logical ‘0’). Further, the access transistor 12 controls reading and writing data to the MTJ 14. A drain (D) of the access transistor 12 is coupled to a bottom electrode 22 of the MTJ 14, which is coupled to the pinned layer 16. A word line 24 is coupled to a gate (G) of the access transistor 12. A source (S) of the access transistor 12 is coupled to a source line 26, which is coupled to a write driver circuit 28. A bit line 30 is coupled to the write driver circuit 28 and a top electrode 32 of the MTJ 14, which is coupled to the free layer 18.
With continuing reference to FIG. 1, when writing data to the MTJ 14, the gate G of the access transistor 12 is activated by activating the word line 24, which couples a write switching current (ISW) (“switching current (ISW)”) from the write driver circuit 28 on the source line 26 to the bottom electrode 22. The ISW provided by the write driver circuit 28 to the MTJ 14 must be strong enough to change the magnetic orientation of the free layer 18. If the magnetic orientation is to be changed from the AP state to the P state, a current flowing from the top electrode 32 to the bottom electrode 22 induces a spin transfer torque (STT) at the free layer 18 that can change the magnetic orientation of the free layer 18 to P with respect to the pinned layer 16. If the magnetic orientation is to be changed from the P state to the AP state, a current flowing from the bottom electrode 22 to the top electrode 32 induces an STT at the free layer 18 to change the magnetic orientation of the free layer 18 to AP with respect to the pinned layer 16.
Because the MTJ 14 is a resistive memory element with a given resistance (RMTJ), applying the ISW to the MTJ 14 during a write operation will generate voltage (VMTJ) across the MTJ 14 according to VMTJ=ISW*RMTJ. However, the ISW should not exceed a defined current level for the MTJ 14, because the MTJ 14 will incur electrical breakdown if the VMTJ generated across the MTJ 14 exceeds a certain breakdown voltage (VBD). With continuing reference to FIG. 1, the MTJ 14 is unable to function as a resistive memory element while in a breakdown state. As the tunnel barrier 20 of the MTJ 14 becomes thinner, breakdown of the MTJ 14 occurs at a lower VBD. Thus, the write driver circuit 28 must generate a strong enough ISW to change the magnetic orientation of the free layer 18 in the MTJ 14. However, a higher ISW may cause the VMTJ across the MTJ 14 to exceed VBD of the MTJ 14, thus causing the free layer 18 in the MTJ 14 to not switch properly. Further, process, voltage, and temperature (PVT) variations that can occur during MTJ 14 fabrication can cause the RMTJ of certain MTJs 14 to be higher, thus increasing VMTJ across the MTJ 14 for a given ISW.
With continuing reference to FIG. 1, the access transistor 12 is not activated by the word line 24 when not writing data to the MTJ 14. However, a leakage current (not shown), occurs in the access transistor 12 when a voltage is applied between the source line 26 and the bit line 30. This undesirable leakage current increases standby power consumption of the MRAM bitcell 10 when not reading or writing data to the MTJ 14.